1. Field of the Invention
The present invention relates to the field of complementary metal-oxide semiconductors (CMOS) devices and more specifically to a CMOS output driver.
2. Prior Art
The use of a complementary metal-oxide semiconductor (CMOS) is well-known in the prior art. The advantages derived from using CMOS technology, which includes lower power consumption, is also well-known in the prior art. Typically, a pair of transistors is coupled in series between a supply voltage and ground, and an output is taken at the junction of the two transistors. The pair of transistors is comprised of an n-type device and a p-type device. In the simplest of operations of a CMOS pair of transistors, one or the other of the transistors is conducting at any given time so that the output, which is obtained at the junction of the two transistors, is coupled through one or the other transistor to the supply voltage or its ground.
Although CMOS devices can operate at a wider range of supply voltages than devices using other types of technology, such as transistor-transistor-logic (TTL), they are susceptible to diode break down or latch-up, if voltages higher than Vcc are applied at the output terminal. High voltages may need to be applied to the output node during special modes of operation. For example, during the manufacturing of these CMOS devices, high potentials may be applied for enabling the devices into a special function or a mode, such as a testing mode. Or in another example, high voltages may be encountered in programming a memory device, such as an electrically programmable read only memory (EPROM). In some instances, an application of high voltage would be desirable at the output node, but because of a possibility of device failure, the high voltage is not applied or severely restricted to prevent such failure of the device. In other instances, the special node voltages are applied at the input (gates of the transistors) to overcome this shortcoming or because pins are not available.
An intent of the present invention is to permit such high voltage application at the output node of a CMOS device.